____________ converts the received optical signal into an electrical signal.

Which of the following does not explain the requirements of an optical detector?

Which of the following detector is fabricated from semiconductor alloys?

The probability of zero pairs being generated when a light pulse is present is given by which of the following equation?

A digital optical fiber communication system requires a maximum bit-error-rate of 10^-9. Find the average number of photons detected in a time period for a given BER.

If the threshold voltage of the pull-down device is higher as compared to the pull up device, the switching threshold (VM) is:

For a static CMOS circuit, there are 2, zero to one transitions for every 4 clock cycles. The value of the activity factor is

For an ideal CMOS inverter operating at a supply of VDD the short circuit power dissipation is maximum at

For an RC switch model, with the on resistance of each device as R and the intermediate load capacitance is C, the delay is then defined as

The propagation delay is a ______ function of fan-in

For an optimised 3-input NAND logic, if the gate size for the three NMOS are M1, M2 and M3, where M1 and M3 are the transistor closet to the ground terminal and power supply respective, then the optimised delay condition is given as

For a ratioed logic, the pull up device is

Which one is not the ideal VTC condition of an inverter?

Pass Transistor Logic is characterised by signal degradation. One of the methods for signal restoration is

Transmission Gate is a good transmitter of

For an n-input dynamic logic the number of gates for full functionality is given as

Which one is not the source of internally generated noise in digital circuit?

If the output and the input capacitance of logic is Cout and Cin respectively then the value of electrical effort is

The time before the rising/falling clock edge till which the data must be stable for proper sampling of the data is referred to as

Which statement is not valid for Pseudo NMOS logic

Cascading negative and positive latches will result in a

Which one is not the design technique for large fan in gate to reduce delay?

Which of the following statement is false for Fully Complementary CMOS Design

Find the value of the logical effort of a NOR-2 gate whose delay is equivalent to a CMOS inverter whose Wp/Wn = 2/1, where Wp and Wn are the widths of the PMOS and NMOS respectively

The interconnect parameter  resistance of a wire increases if